module key_scan(clk,rst,key_in,flag);
input  clk,rst;
input  key_in;
output reg flag;
 
reg [25:0] cnt;
 
always@(posedge clk,negedge rst) begin 
  if(!rst)
    cnt<=0;
  else if(key_in)
    cnt<=0;
  else if(cnt==1000_000 && key_in==0)
    cnt<=cnt;  
  else
    cnt<=cnt+1;
end
	 
always@(posedge clk,negedge rst) begin
  if(!rst)
    flag<=0;
  else if(cnt==1000_000-1)
    flag<=1;
  else
    flag<=0;	 
end
 
endmodule