module top(clk,rst,key,led);
 
input clk,rst;
input [2:0] key;
output reg[3:0] led;
 
second   U1(clk,rst,1000,sec);
key_scan U2(clk,rst,key[0],k0);
key_scan U3(clk,rst,key[1],k1);
key_scan U4(clk,rst,key[2],k2);
 
always @(posedge clk,negedge rst) begin
  if(!rst)
    led[0]<=1;
  else if(sec)
    led[0]<=!led[0];
end
 
always @(posedge clk,negedge rst) begin
  if(!rst)
    led[1]<=1;
  else if(k0)
    led[1]<=!led[1];
end
 
always @(posedge clk,negedge rst) begin
  if(!rst)
    led[2]<=1;
  else if(k1)
    led[2]<=!led[2];
end
 
always @(posedge clk,negedge rst) begin
  if(!rst)
    led[3]<=1;
  else if(k2)
    led[3]<=!led[3];
end
 
endmodule