特性 Feature
- 最低成本低功耗的CPLD
- Lowest Cost and low-power CPLD
- 快速启动、非易失性标准兼容架构。
- Instant-on, non-volatile standard compatible architecture.
- 全局时钟网络中最多有 4 条全局时钟线，贯穿整个设备。
- Up to 4 global clock lines in the global clock network that drive throughout the entire device.
- 提供可编程的快速传播延迟和时钟到输出的时间。
- Provides programmable fast propagation delay and clock-to-output times.
- 为每个设备提供PLL功能、时钟倍增和相位偏移。
- Provides PLL per device, clock multiplication, and phase shifting.
- 包含4个嵌入式块内存（EBR）M9K，可配置为提供多种内存功能，如RAM、移位寄存器、ROM和先进先出（FIFO）。
- Contains 4 Embedded Block RAMs (EBRs) M9K, that can be configured to provide various memory functions, such as RAM, shift registers, ROM, and FIFO.
- 支持3.3伏逻辑电平
- Supports 3.3-V logic level
- 可编程斜率、驱动强度、母线保持、可编程上拉电阻、开漏输出、施密特触发器和可编程输入延迟。
- Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
- 内置联合测试行动组（JTAG）边界扫描测试（BST）电路，符合 IEEE Std. 1149.1-1990 标准。
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
- 符合IEEE Std. 1532标准的ISP电路
- ISP circuitry compliant with IEEE Std. 1532
- 片上振荡器支持最高8 MHz的频率
- On-Chip oscillator is provided to support frequency to 8 MHz
- 3.3伏LVCMOS和LVTTL标准
- 3.3-V LVCMOS and LVTTL standards
PDF